Description
Cambridge, UK | Full-time or Part-time | Permanent | Salary: £62,000 to £80,000 DOE
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlaneâs mission is to make quantum computing useful, sooner. From climate change to healthcare, large and reliable quantum computers will help solve some of the worldâs important challenges. Riverlane is building the quantum error correction stack to make this happen. Itâs a complex problem that requires a range of skills, talent and passion. Weâre making remarkable progress and growing fast.â¯
About the role
We have a fantastic opportunity for an experienced Digital Design Engineer to join us as we build the worldâs first quantum error correction (QEC) stack.⯠Donât have a background in quantum computing?⯠Not a problem!⯠This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills.⯠You will learn quantum computing along the way.â¯â¯
As a Digital Design Engineer at Riverlane, you will help develop a multi-FPGA, low-latency, high throughput system that needs to perform complex operations, in a predictable and guaranteed way.â¯
Our mission is exciting, but complex.⯠It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions.â¯â¯â¯
You will thrive in an environment where knowledge sharing and continuous learning are the norm.⯠We are moving fast in a brand new market, where requirements can change as the technology evolves, so the ability to adapt is important.â¯
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What you will do
As a Digital Design Engineer at Riverlane, you will work on one of these key areas:â¯
Implementation of QEC decoders on hardware;â¯
Implementation of low-latency, high throughput data movement between cards and IPs; orâ¯
Design of low-latency interfaces to bring data in the systems.â¯
In all of the above, you will (often from scratch) design or integrate complex IPs and develop tests, collaborating closely with our Software, Verification and Testing experts to deliver an outstanding product.â¯â¯â¯
Requirements
What we need
Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
Experience of (in either academic or industrial settings) at least one of the following:
Customisation of RISC-V CPUs e.g. addition of new instructions and associated hardware accelerators;
Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo-codes;
Architecture of System on Chip solutions with at least one CPU and custom accelerators
Proven capability to test, debug and improve complex systemsâ¯
Capability to convert product requirements into technical specifications to document and share your workâ¯
A curious nature and a passion for learning and continuous improvementâ¯
Excellent communication skills with the ability to work both independently and collaboratively as part of a teamâ¯
Benefits
What you can expect from us
A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more)
Equity so that our team can share in the long-term success of Riverlane
28 days annual leave (plus bank holidays) and enhanced family leave
A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities
A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget
